Abstract
We present a new simple form window function with application to FIR filter design, which has superior performance compared to the several commonly used windows. The new window is almost equiripple. For sufficient value of our tuning parameter, the proposed window has the main lobe width less than that of the commonly used Hamming window, while featuring 10~17 dB smaller side lobe peak. For lower window lengths, the performance of Hamming window is degraded, while the new window maintains its maximum side lobe peak about -45~-55 dB compared to -37~ -39 dB of Hamming window, and at the same time offers smaller main lobe width. Our results also show substantial performance improvement of the proposed window compared to the Hanning, Kaiser, and Lanczos windows. A performance comparison of the proposed and Dolph-Chebyshev windows is also presented. The designed FIR filters confirm the efficiency of the new window.
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In this paper window shape parameter ‘α’ in Planck-Bessel and Kaiser Window functions on the Signal to Noise Ratio (SNR) values of the Indian Mesosphere-Stratosphere-Troposphere (MST) radar is computed. The six sets of multibeam observations made by the MST radar in lower atmosphere are analyzed for results. The echo samples of the in-phase and quadrature components of radar in Fourier transformation are weighted with the new adjustable window based on the Planck-Bessel Window function. The effects of data weighting with the change of the window shape parameter ‘α’ of the Planck-Bessel and Kaiser Window functions are given in it. It is observed that the increase of shape parameter increases the signal to noise ratio values and a better improvement is reported. For Planck-Bessel and Kaiser Window functions are proposed to analyse the MST radar return signals to obtain optimum values of the shape parameter ‘α’. Due to the effect of side lobe reduction, the result gives the improvement of SNR of noisy data and demands for the design of optimal window functions.
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Image scaling is a very important technique and has been widely used in many image processing applications. In this paper, we describes and analyzes the image scaling algorithm for a coprocessor unit with NIOS II processor. The main objective of this paper is to replace the existing image processing methods for scaling an image using a novel image scaling algorithm. The performance of NIOS II processor is improved by deploying a coprocessor unit for image scaling operations. The image scaling algorithm will be ported onto the Altera NIOS II processor which will be a pure software implementation then a image bilinear scaling will be designed in hardware. This hardware filter will be interfaced to NIOS II processor as coprocessor. Finally through hardware synthesis we compare the parameters of our method with previous methods.
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This paper reports on Automated Parking slot. Automated Parking slot helps in the regulation of any parking slot with the large number of vehicle involved. This project concentrates on less manpower utilisation, less installation and maintenance cost. This project is a versatile project which can be implemented on any condition and location. This is a conceptual project and just a prototype was designed and hence can go through the various stages of modification to make it reliable and much more suitable for the real time applications.
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This paper describes the 8051 microcontroller interrupts concepts, programming and applications. The applications include an interfacing of LEDS, STEPPER MOTOR, DC MOTOR and SERIAL PORT with micro controller and these are controlled by external interrupts (INT0, INT1) signals through switches. In this experiment P89V51RD2 8-bit microcontroller is used to program the interrupts to flash LED’s, rotate the stepper motor and DC motor through clockwise and anti-clock wise directions. The Hardware description and software developments are presented in this paper.
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This paper proposes the design of VLSI architecturefor image compression. To perform the process of image compression VLSI architecture is designed using lifting based discrete wavelet transform (DWT) and it is implemented in Spartan 3EDK kit. The lifting based DWT architecture has the advantage of lower computational complexities and higher efficiencies. Through the DWT, signals can be decomposed into different sub bands with both time and frequency information. Traditional DWT architectures are based on convolutions. Then, the second-generation DWTs, which are based on lifting algorithms, are proposed .Compared with convolution-based ones; lifting-based architectures not only have lower computation complexity but also require less memory. Here we designed core processor Microblaze and implemented using XILINX platform studio Design suite. The algorithm is written in system C Language and tested in SPARTAN-3 FPGA kit by interfacing a test circuit with the PC using the RS232 cable. In this proposed system, the coprocessor Microblaze is converted into a lifting based DWT architecture. The test results are seen to be satisfactory. It can overcome the shortages in previous works and high speed in processing for higher applications.
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The RS-485 serial protocol is serial communication protocol which specifies bi-directional and half-duplex data transmission up to N nodes. A Serial Communications Interface (SCI) is a device that enables the serial (one bit at a time) exchange of data between a microprocessor and peripherals. In this respect, it is similar to a Serial Peripheral Interface (SPI). But in addition, the SCI enables serial communications with another microprocessor or with an external network. This paper deals with design of serial communication interface IP core in RS485 communication protocol which is modeled using Verilog HDL and is simulated in ModelSim®. The design has been synthesized using Altera Quartus® and emulated using Altera Cyclone®.
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PMBLDC motors are gaining a lot of popularity due to their high efficiency as the Permanent Magnets do not carry current which results in negligible copper losses as compared to asynchronous motors. This paper introduces a design for speed control of the PMBLDC motor using multilevel dc link inverter fed by a Boost Converter. The multilevel dc link inverter consist of five level voltage sources, which are controlled by switches. The motor can be driven at different speed level as per its load requirement by making use of five level MLDC Link Inverter. In case of traditional inverter which is only a one level inverter the speed cannot be controlled as per the load requirement. The MLDC link inverter provides the output voltage waveform in step shape form. Thus as the number of cells (n) increases output voltage touches the fundamental component. The input voltage is low, thus to increase the input voltage given to the MLDC link inverter the (Boost Converter) has been designed. The Boost Converter is placed in between (DBR)Diode Bridge Rectifier and (MLDCLI). Both the design and results of Single level inverter and Multilevel Dc Link Inverter are obtained and compared by using the MATLAB Software along with the use of Simulink and Simpower system Tools.
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Cryptographic algorithms are required to provide data security during its transmission through insecure channels. The IDEA NXT algorithm formerly known as FOX is a recently developed algorithm which provides high levels of security, performance and can be efficiently implemented in hardware and software. IDEA NXT is a symmetric (private key) block cipher with a strong and efficient key schedule algorithm. Its high level structure is based on Lai-Massey scheme. The implementation of standard IDEA NXT with a block of 64-bits data, key of 128-bits and 16 rounds is discussed in this paper.The designs were modelledusing Verilog HDL, simulated using Modelsim® and prototyped in Xilinx’s platform FPGA.
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Orthogonal Frequency Division Multiplexing (OFDM) is a very attractive technique for multicarrier transmission and has become one of the standard choices for high speed data transmission over a communication channel. An extension of OFDM to accommodate multiple simultaneous users is the Orthogonal Frequency Division Multiple Access (OFDMA). A well-known drawback of this multicarrier transmission is its inherited large peak-to-average power ratio (PAPR). This paper uses a different method to solve the PAPR problem in OFDMA, which is based on the transformation of signal using Phase Modulation (PM). The discrete Fourier transform in traditional DFT-OFDMA systems are replaced by a discrete cosine transform (DCT), the resulting DCT-OFDMA system is then used to develop an OFDMA system called Phase modulated DCT based OFDMA (DCT-OFDMAPM). Phase modulation based systems have the advantage of Constant Envelope (CE) signals and the ability to improve the diversity of multipath environment. The goal of this paper is to compare Bit error rate (BER) performance of the DCT-OFDMAPM system as well as the traditional DFT-OFDMA system for different subcarrier allocation scheme. The simulation result shows that DCT-OFDMA-PM with interleaved subcarrier mapping outperforms in terms of BER and PAPR.
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This paper presents FSM baseddesign of a Reconfigurable Sequence detector which detects the bit sequence having any number of bits i.e. (from 2 to 8). Also the bit pattern is Reconfigurable i.e. the bit pattern is selected by user and whenever that particular bit pattern is found in incoming bit stream the system will detect that bit pattern. This paper provides a synthesizable reconfigurablesequence detectorip core which can be made available as COTS for a variety of applications involving SoC integration. This design is implemented inVerilog HDL and simulated in ModelSim®. The design is synthesized using Altera® Quartus II and functional hardware testing is done on FPGA.
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The MESI coherence controller is a coherence system controller that supports the MESI coherence protocol and synchronizes the memory requests of the system masters to keep the consistency of the data in the memory and in the local caches. A coherence system contains several elements that together enable the data consistency. The major elements of the coherency mechanism are coherency controller, coherency masters and coherency buses. This paper deals with the design of MESI coherency controller block which is modeled using Verilog HDL and is simulated in ModelSim®. The design has been synthesized using Altera Quartus® and emulated using Altera Cyclone®.
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In this paper we present the Modified Adaptive threshold bit flipping algorithm for decoding of LDPC code, the above algorithm replace the delay-inducing global minimum operation with adaptive threshold value. Through simulation the decode improves error correcting performance and reduces the number of iterations which are close to shannon’s limit, in addition to that the message passing technique and simpler decoding strategy makes the Hardware implementation feasible.
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A compact printed Ultra Wideband (UWB) monopole antenna with dual band-notched characteristics is presented. The proposed design consists of a rectangular radiating patch and partial ground plan, by using this element as a double variable slot in form of T, to cross the plan of mass, we have a several resonances and a band – width is increased up to 121%. We use a parasitic structure in form of E and U reversed, respectively, instead of suitably changing dimensions of these elements in a coupled capacitive way. The results of simulations show that the antenna made offer a very great band-with from 2.8 to 11.4 GHz defined by return loss – 10 dB, with two notched bands, covering the WLAN and WiMAX. We talked over the adaptation of the antenna, the diagrams of radiation and the profit. The antenna proposed is optimized by ANSOFT High Frequency Structure Simulator (HFSS).
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The aim of this paper is to design a uniform I-shaped microstrip antenna with enhanced bandwidth suitable for C-band applications operated at central frequency of 6.75 GHz. The C-band and its slight variations contain frequency ranges that are used for many satellite communication transmissions, some Wi-Fi devices, cordless telephones and weather radar systems. For satellite communication, the microwave frequency of the C-band perform better under adverse weather conditions in comparison with Ku band (11.2GHz to 14.5GHz) microwave frequency, which are used by another large set of communication satellites. An I-shaped microstrip antenna designed with dual notches is resonating at central frequency 6.75GHz with a gain of 2.60dBi 22.12% bandwidth and directivity 10.44dBi directivity. The antenna covers the 6.31GHz to 7.90 GHz band for C-band applications. The antenna designed on FR4 substrate, that had a relative dielectric constant 4.4, a loss tangent 0.025 and thickness h=1.6mm.
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This paper reveals how periodicity of a two dimensional array depends on resonant frequency and bandwidth. Primarily the periodicity is 0.032m in both x and y direction. Then periodicity in x direction is increased upto0.06m and corresponding resonance frequency and bandwidth characteristics have been studied. Similarly out of 29(0.032m to 0.06m) possible values of periodicity in y direction the same procedure is repeated for five different values and corresponding graphs has been investigated.
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A force obliged differentiation improvement calculation for emissive showcases dependent upon Histogram Adjustment (HE) is proposed in this paper. We first propose a log-based histogram change plan to lessen overstretching ancient rarities of the traditional HE procedure. At that point, we create a force utilization model for emissive shows and form a goal capacity that comprises of the histogram-adjusting term and the force term. By minimizing the destination capacity dependent upon the raised enhancement hypothesis, the proposed calculation accomplishes contrast improvement and force sparing at the same time. Additionally, we stretch out the proposed calculation to upgrade feature successions, and also still pictures. Reproduction outcomes exhibit that the proposed calculation can decrease power utilization altogether while enhancing picture contrast and perceptual quality.
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The most significant feature of diagnostic medical images is to reduce Gaussian noise, and salt and pepper noise which is commonly found in medical images and make better image quality. In recent years, technological development has significantly improved analyzing medical imaging. This paper proposes different hybrid filtering techniques for the removal of Gaussian noise, and salt and pepper noise. Noise is an important factor which when get added to an image reduces its quality and appearance. So in order to enhance the image qualities, it has to be removed with preserving the textural information and structural features of image. There are different types of noises exist who corrupt the images. Selection of the denoising algorithm is application dependent. Hence, it is necessary to have knowledge about the noise present in the image so as to select the appropriate denoising algorithm. Objective of this paper is to present brief account on types of noises, its types and different noise removal algorithms. In the first section types
of noises on the basis of their additive and multiplicative nature are being discussed. In second section a precise classification and analysis of the different potential image denoising algorithm is presented. At the end of paper, a comparative study of all these algorithms in context of performance evaluation is done and concluded with several promising directions for future research
work.
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