IJECT 7.4 Ver -1 (Oct-Dec 2016)

INTERNATIONAL JOURNAL OF ELECTRONICS & COMMUNICATION TECHNOLOGY (IJECT)-Vol 7.4 Ver 1(Oct-Dec 2016)


International Journal of Electronics & Communication Technology Vol 7.4 Ver 1 (Oct-Dec 2016)
S.No. Research Topic Paper ID
01 Power Flow Improvement in Transmission Line Using UPFC
Jalla Pavan Sai Kumar Reddy, Prasad Janga

Abstract
This paper proposes a brand new real and reactive power coordination controller for a Unified Power Flow Controller (UPFC). The fundamentalcontrol for the UPFC is such that the series converter of the UPFC controls the transmission line real/reactive power flow and the shunt converter of the UPFC controls the UPFC bus voltage/shunt reactive power and the DC link capacitor voltage. In constant state, the real power demand of the series converter is offered with the aid of the shunt converter of the UPFC. To prevent instability/lack of DC link capacitor voltage for the duration of transient conditions, a new real power coordination controller has been designed. The need for reactive power coordination controller for UPFC arises from the fact that excessive bus voltage (the bus to which the shunt converter is hooked up) excursions occur throughout reactive power transfers. A brand new reactive power coordination controller has been designed to limit excessive voltage excursions throughout reactive power transfers. Matlab simulation results had been presented to exhibit the improvement in the efficiency of the UPFC manage with the proposed actual power and reactive power coordination controller.
Full Paper
IJECT/74/1/A-450
02 Implementation of Baugh Woolley Multiplier by Using Novel Design RTP Reversible Logic Gate
M.Ravindrababu, K.Satyanarayanaraju

Abstract
High speed and low power consumption are key requirements in any VLSI design. Conventional digital circuits dissipateenergy (KT ln2 joules/kelvin) as a bit of information is lost during the operation. Due to its low power dissipation, reversible logic circuit is more effective than conventional digital circuit. Reversible logic plays an important role in any low power circuit design. This paper presents a work on implementation of Baugh Woolley multiplier based on reversible logic gate technology. The structure of reversible gate Baugh Woolley multiplier consists of a Toffoli gate and an RTP reversible logicgate. The power dissipation of RTP gate full adder is less when compared to conventional full adder. The Baugh Woolley reversible multiplier is implemented in CMOS 0.13μm 1P2M technology has good performance in power dissipation when compared with other researches.
Full Paper
IJECT/74/1/A-451
03 PAPR Reduction in OFDM Systems with Various Point FFTs
Shivani Gupta, Prof. Rahul Makrariya, Dr. M. Fatima

Abstract
Orthogonal Frequency Division Multiplexing (OFDM) is considered to be a promising technique against the multipath fading channel for wireless communications. However, OFDM faces the Peak-to-Average Power Ratio (PAPR) problem that is a major drawback of multicarrier transmission system which leads to power inefficiency in RF section of the transmitter. This paper presents different PAPR reduction techniques and concludes an overall comparison of these techniques. Simulated results are also included for the modulation technique (BPSK, QPSK) with different point FFTs.
Full Paper
IJECT/74/1/A-452
04 Design of IEEE 1149.1 Testing Bus Controller IP Core
C. Pavani Reddy, Katta Vani

Abstract
This paper introduces the design and implementation of a testing module based on the fundamentals of the IEEE 1149.1 Boundary- Scan (BS) standard. The presented module illustrates the usage of the IEEE 1149.1 standard for in-circuit interconnect testing thereby increasing observability and controllability for single/ multiple devices. The module covers the standard architecture, protocol, and required instruction sets. It includes a TAP controller, scan register, other Boundary Scan registers necessary to execute the BS commands like: EXTEST, BYPASS and SAMPLE/ PRELOAD. Furthermore, it provides information and animated boundary-scan test simulations. The presented work is divided into two main parts; software creation and hardware implementation. The user-friendly software module presents the ability to perform the mandatory testing operations in the BS standard in order to validate the hardware reliability. The hardware implementation is a complete design of the BS architecture together with a circuit under test.
Full Paper
IJECT/74/1/A-453
05 Study of Effective Dielectric Permittivity and Capacitance for Finite Dielectric Thickness Coplanar Waveguide
Shanu Sharma, Alok Kumar Rastogi

Abstract
At higher frequencies microwave and millimeter wave transmission lines play an important role .Among all transmission lines CPW is rapidly becoming salient substitute due to its uniplanar geometry. In this paper simulation and Analysis (quasi static analysis using conformal mapping) of FCPW (Finite dielectric thickness Coplanar Waveguide) on Alumina and Roggers substrate with varying height of substrate are analyzed. The effect of Capacitance and effective permittivity on aspect ratio is also analyzed. Simulations are carried out on SONNET software; it is based upon Method of Moments principle and gives excellent simulations which are consistent with actual fabrications. This paper will help to optimize the design and fabrication of the FCPW for various dedicated applications.
Full Paper
IJECT/74/1/A-454
06 A Printed Monopole Antenna for TV White Space Applications
Ghulam Ahmad Raza, Garima Saini

Abstract
In this paper a printed monopole antenna is presented for TV white spaces applications. The shape of the antenna is based on the shape of a wine glass. The overall dimension of the antenna is 170mm x 120 mm x 1.6 mm. It is designed using FR4 substrate which makes it low cost and light weight. The antenna shows wider bandwidth coverage from 495 MHz to 1540 MHz (1045 MHz). Simulated results are presented and discussed in this paper. The proposed antenna is suitable candidate for its use for TV white space communication devices.
Full Paper
IJECT/74/1/A-455
07 Design and Simulation of Compact Microstrip Patch Antenna by Using Metamaterial for WLAN
Ruchi Thakur, Sunayana

Abstract
In this paper development and design of microstrip patch antenna with SRRs (Split Ring Resonators) and Rods are introduced. To enhance better performance of microstrip patch antenna SRRs and rods are used. Metamaterial technique is used for designing. Substrate FR-4 is used which has dielectric constant 4.9. The results of return loss and VSWR are far much better. The return loss of microstrip patch antenna at operating frequency 4.864 GHz is -25.688 dBi and VSWR is 1.109. The simulated and measured results of the proposed antenna are obtained by using CST Software.
Full Paper
IJECT/74/1/A-456
08 Semi-Circular Micro Strip Patch Antenna for Multi-Frequency Application
Dr. A. Prathap Kumar, G.Vishnu Kanth

Abstract
A Semicircular Microstrip patch antenna is simulated. Three different bands of operation are achieved. All the bands of operation are independent to each other. All the bands have good Return Loss, VSWR and Radiation resistance. The outer dimensions of the patch are designed so that the antenna resonates at the lower resonant frequency. The dimensions of the slots are designed to control the upper resonant frequency and the bandwidth. Some other circular and semi circular antenna are also simulated for a thorough characterization of the antenna.
Full Paper
IJECT/74/1/A-457
09 Design and Performance Analysis of Wide Band Circularly Polarized EBG Microstrip Antenna for Base Station Applications
Krishnananda, Dr. T S Rukmini

Abstract
Over the past decades, there is a rapid growth in development of various EBG antennas. The performance of all such EBG antennas depends on the design and proper selection of the antenna dimensions. This paper presents design of two antennae and their performance analysis. The best performed antenna is fabricated and results are validated. The proposed antenna is designed at 2.4GHz which is suitable for GPS and base station applications. The fabricated antenna provides circular polarization with wider bandwidth.
Full Paper
IJECT/74/1/A-458
10 Low-Power Differential SRAM design for SOC Based on the 25-um Technology
Sivaprasad Godugunuri, Naveen Dara, SambasivaNayak R

Abstract
In recent, the SOC styles area unit the vastly complicated styles in VLSI these SOC styles having important low-power operations problems, to comprehend this we tend to enforced low-power SRAM. However, these SRAM Architectures critically affects the entire power of SOC and competitive space. To beat the higher than disadvantages, during this paper, a low-power differential SRAM design is planned. The differential SRAM design stores multiple bits within the same cell operate at the minimum in operation low-tension and space per bit. The differential SRAM design designed supported the 25-um technology using Tanner-EDA Tool.
Full Paper
IJECT/74/1/A-459
11 Design and Development of Ultrasonic and IR Insect Detector for Oilseeds Crop
Kanishk Sisodiya, Mandeep Singh

Abstract
In India each year, insects cause a massive economic loss. Hidden swarm of insects attacks plants slowly but it cause enormous loss in agriculture field. If, however, these insects can’t be detected in their early stage and farmer could use the pesticides and insecticides without knowing whether insects are there or not. Then this could
decrease the economical state. This paper presents the design of an Ultrasonic insect detector that comprises of an ultrasonic sensor, an infrared sensor and a GSM module in which ultrasonic sensor will detect the sound of insects by detecting ultrasonic signals generated by the feeding event of insects in crops. After that the presence of insects will be confirmed by the heat radiated by the insect’s body through infrared sensor. Once the presence of insect is confirmed by both the sensors a message will be sent by using GSM module in which it will inform the farmer about the presence of insects after that farmer can use pesticides or insecticides according to their crops. This research not only helps the farmers but also increase the agriculture productivity.
Full Paper
IJECT/74/1/A-460
12 A Survey on Low Power CAM Circuits and Architectures
M.V.S.R.Kishore, Dr. B.L.Raju, Dr.D.Srinivasarao

Abstract
We survey recent advancements in theoutline of vast limit content addressable memory (CAM). A CAM is a memory that implements the search table function in a single clock cycle using committed evaluation circuitry. CAMs are particularly prominent in community routers for packet forwarding and packet classification; however they are additionally in a sort of other purposes that require fast table query. The fundamental CAM-design project is to decrease energy consumption related to the huge quantity of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM-plan procedures the circuit levels and at the architectural units. At the circuit level, we review lowenergy matchline sensing schemes and at the architectural level we survey four approaches for reducing power consumption like bank selection scheme, static divided matched line architecture, Butterfly ML TCAM and MSML based CAM.
Full Paper
IJECT/74/1/A-461
13 Efficiency of 3D-DCT in Improving Video Quality
P.Sharmila Rani, Dr. K.Soundara Rajan

Abstract
The paper presents a comparison of adaptive three dimensional discrete cosine transform (3D-DCT) based motion level prediction algorithm which finds the optimal cube for 3D-DCT based compression technique by analyzing the motion content of the video sequence, Normalized Pixel Difference and Variable Temporal length algorithms. Peak Signal to Noise Ratio (PSNR) has been taken as measurement in identifying the quality of video. It is proved Experimentally that instead of motion compensation technique, the 3D-DCT based motion level prediction algorithm gives better performance in terms of reduction in the data rate andimproves the encoding process.
Full Paper
IJECT/74/1/A-462
14 A Reduced Size Rectangular Patch Antenna
Chandrani Chakravarty, Dr. Partha Pratim Sarkar

Abstract
A rectangular patch microstrip antenna with slot loaded ground plane is represented in this article. By embedding slots in the antenna’s ground plane, it is observed that the resonant frequency of the microstrip antenna is significantly lowered, which can lead to a large antenna size reduction for a fixed frequency operation. The proposed microstrip antenna has rectangular slots on its ground plane which reduces its size by 84%and resonance frequency reduction by 74% compared to the conventional patch antenna. Antenna is simulated using Ansoft designer version 2.2.0; the antenna is fabricated on FR4 epoxy substrate.
Full Paper
IJECT/74/1/A-463