Vol 3 Issue 4-1



 

INTERNATIONAL JOURNAL OF ELECTRONICS & COMMUNICATION TECHNOLOGY (IJECT)-VOL III ISSUE IV, VER. 1 OCT. TO DEC. 2012


International Journal of Electronics & Communication Technology Vol. 3 Issue 4, Ver. 1
S.No. Research Topic Paper ID
   1 An Efficient Mining Model For Enhancing Text Classification
Mahesh Kadiyala, G Jacob Jayaraj

Abstract

Text classification is a supervised technique and it uses labeled training data to learn the classification task and then automatically classifies the test text documents using the learnt system. In information retrieval and management task categorization plays a vital role. The procedure of text categorization includes the sequence of the steps text preprocessing, feature extraction and then classification. In our task, two machine learning algorithm (Naïve Bayes and KNN) are used for categorization. This work includes some noise reduction techniques to reduce the dimensionality of feature vector that improves the efficiency of categorization. For better categorization each document had undergone by some feature weighting and reduction techniques for the enhancement of the classification task. After that, the classifier trained by self made data set and the results analyzed by Reuters corpus document set.
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IJECT/34/1/
A-476
   2 A Study Based Research Paper on Speech Processing and Speaker Identification Using Matlab
Yashika Vijureja, Mayur Sharma

Abstract

Speaker Identification is a process to recognize someone by their voice. The goal of speaker identification is to extract, characterize and recognize the information about speaker identity. In this paper, we will discuss the Artificial Neural Network (ANN) approach to speaker identification system. The proposed system comprises three main modules, a feature extraction module to extract necessary features from speech waves, a Vector Quantization (VQ) module to generate the speaker codebook and an ANN module to classify the speakers based on their high discriminative power. The proposed intelligent learning system has been applied to a case study of text-dependent speaker identification system and the performance is evaluated by applying two types of feature extraction techniques: Mel Frequency Cepstral Coefficients (MFCC) and Linear Predictive Cepstral Coefficients (LPCC). Experiment shows that the new proposed system the characteristic vocal information included in speech provides significantly higher performance compare to conventional method.
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IJECT/34/1/
A-477
   3 Antenna Miniaturization using Magneto-Dielectrics
Rajendra R. Patil, Vani R.M, P. V. Hunagund

Abstract

In this paper, we demonstrate miniaturization of antenna using magneto-dielectric nanocomposite material having permittivity and permeability values higher than one. Zinc ferrite epoxy nanocomposite layer validates the use of such material for antenna miniaturization over patch of the probe fed Microstrip Patch Antenna (MPA). The loaded magneto-dielectric material shifts the resonance frequency of the base antenna to lower frequency thus demonstrating the capability of miniaturization. The fractional frequency change can be used to design antennas with magnetodielectric cover at specific operating frequency.
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IJECT/34/1/
A-478
   4 Single Band Microstrip Patch Antenna for WiMAX Applications
Parminder Singh, Amandeep Sharma, Avinash Kaur, Amandeep Kaur

Abstract

Microstrip patch antennas have been widely used in a various useful applications, due to their low weight and low profile conformability, easy and cheap realization. In this paper, an attempt has been made to investigate new microstrip antenna structure for WiMAX system Applications. CST MWS and MATLAB Softwares are used for the simulation and design calculations of the microstrip antennas. The return loss, VSWR, Directivity, gain, radiation pattern are evaluated. Using CST MWS simulation software proposed antenna is designed/simulated and optimized. The antenna exhibits a single band from 5.47 GHz to 5.85 GHz covering the WiMAX bands.
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IJECT/34/1/
A-479
   5 The JPEG Digital images based on Stenographic Method
G. Gangaram, K. SamPrasad, M. Srinivasa Rao

Abstract

The paper puts forward a novel Steganography method based on the JPEG digital images Instead cover-image into 8×8 blocks, non-overlapping blocks of 16×16 pixels is used. With our proposed quantization table, The DCT coefficients are quantized and embedded the secret messages. The experiment results show that our method has the larger Steganography capacity and better stego-image Quality than the other methods.
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IJECT/34/1/
A-480
   6 A VHDL Based Floating Point ALU for DSP Processing
K. Niranjan Reddy, D. Sri Harsha, S. Sri Vani, S. Tarun Prasad

Abstract

Many DSP techniques depend upon exclusive floating point arithmetic for the dynamic range of operations which require millions of calculations per second. Digital signal processing of 1d and 2d signals need different mathematical calculations which are mainly of complex data. Operations like FFT, Z Transform constantly requires various Exponential Arithmetic. Such computationally challenging techniques need computational acceleration using Custom Computing Machines (CCMs) being designed exclusively for the application. Floating point operations require excessive memory and time for conventional implementations. Therefore, custom formats for individual applications like DSP are more feasible on CCMs, and can be easily designed and implemented on a fraction of a single FPGA. VHDL, facilitates the design and development of custom operations without effecting the performance. Most of the processor architectures are built to handle real and non exponential data. Even though there are several architectures proposed over the years to explicitly handle exponential arithmetic, none are targeted for a specific DSP operation based on exponential arithmetic. In this paper we propose design of a unique exponential arithmetic unit for exponential addition.
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IJECT/34/1/
A-481
   7 Video Softphone using Gstreamer and Sofia-Sip on DTV Platform
Neetu Gupta, Tarun Maheshwari

Abstract

The objective of this paper is to propose idea of video phone client using gstreamer media manager, Sofia-sip client on smart TV platform. Smart TV uses an ARM board which provides high quality codecs and high definition camera support. Gstreamer provides platform for creating audio and video pipelines. Sofiasip is used for SIP signaling. Sofia-SIP implementation follows RFC3261 and related key RFCs.
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IJECT/34/1/
A-482
   8 Spread Spectrum using Chaotic System
Nandini Pathak, Rinkoo Bhatia

Abstract

Chaotic signal helps in a secure communication, by generating wideband spectra of random sequences. Chaotic signal has the property of synchronization; data are transmitted from one location to another by mapping bit sequences to symbols, and symbols to sample functions of analog waveforms. The synchronization between two digital chaotic oscillators, serving as a transmitterreceiver scheme, is studied. Chaotic digital communication system based on chaotic signal generation, chaotic modulation, chaotic differential peak keying, interleaved chaotic differential peak keys. At the receiver, the symbol may be recovered by means of coherent detection, where all possible sample functions are known, The oscillators exhibit rich chaotic behavior and are unidirectional coupled, forming a master-slave topology. Chaotic signal generation where an oscillator based on linear system isused to generate random signals which are highly deterministic in nature. A chaotic circuit to generate chaotic signal, A/D converter, D/A converter and a digital processing mechanism to control all signal flows and perform I-CDPK modulation corresponding to input digital bits. The system output is sent to ICDM’s chaotic circuit through both transmitter and receiver.
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IJECT/34/1/
A-483
   9 Design of Low Power 6th Order Gm-CAnalog Filter for GSM Receiver
Sudarshan Malasha, Anshul Jain, Jitendra Singh Barsena, D. S. Ajnar, Pramod Jain

Abstract

This paper introduces a CMOS low-power band pass analog filter For GSM Receiver applications. A linear and tuneable CMOS Transconductance (Gm)-C bandpass filter structure realized by the cascading of 3 stages of a new proposed biquads for gyrator stages.AGmbiquad istuneable for gain and frequency selection of the channel in GSM. The centre frequency is 70 MHz with a 3-dB bandwidth of 180 KHz. The power consumption is 576mW with a single 1.8V supply. The filter is simulated in 0.18µm Cadence environment. In addition, the filter can be programmed in order to process GSM signals, while a little area overhead is required for automatic tuning and selection purposes.
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IJECT/34/1/
A-484
   10 Low-Power and High-Speed CMOS Circuits using Leakage Reduction Techniques
B. Dilip, Y. Alekhya, U. Sandhya Rani

Abstract

As the technology scales down, the down scaling of threshold voltage takes place, resulting in the increase of the sub-threshold leakage current. In CMOS circuits, the sub-threshold leakage current is the dominant factor while considering the static power. Reducing the leakage current reduces the static power. LECTOR is a leakage control technique for designing low leakage power CMOS logic circuits. The advantage with LECTOR compared to other leakage reduction techniques is not affecting the dynamic power. MTCMOS, a technique to achieve speed increment in addition to low power, is used for those circuits which have critical path. This paper analyses the leakage current and the propagation delay in LECTOR and MTCMOS based CMOS circuits using nanoscale technology.
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IJECT/34/1/
A-485
   11 Design of OTA for Gm-C Filter
Sudarshan Malasha, Kaushal Dhamaniya, Rajendra Muzalda, D. S. Ajnar, Pramod Jain

Abstract

This paper presents design of operational transconductance Amplifier. This design is developed and simulated in 0.35µm CMOS Tanner Environment. This OTA having a biasing current of 2.2 µA with supply voltage ±1.8 V.Simulated Result of this OTA shows the open loop gain of about 60 dB , CMRR 78dB and PSRR of 82dB. This OTA having power dissipation of 7.6 mW and Slew Rate 2.0 V/µsec.
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IJECT/34/1/
A-486
   12 Improved Palmprint Recognition using 2D Gabor Analysis
N K Mittal, Mohd Ahmed, Farha Naaz

Abstract

Palmprint Recogntion system inherently implements many of the same matching characteristics that have allowed fingerprint recognition to be one of the most well known and best publicised biometric Technologies. Both palm and finger biometrics are represented by the information presented in the friction ridge impression. This information combines ridge flow, ridge characteristics, and ridge structure of the raised portion of the epidermis. Various palmprint recognition mechanisms have been proposed before. This paper discusses the realisation, of an improved palmprint feature extraction and matching mechanism using 2D Gabor Filters which results in reduced FMR and FNMR.
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IJECT/34/1/
A-487
   13 Dual-Band Size Deducted Slotted Patch Antenna for Application in Microwave Communication
Arnab Das, Bipa Datta, Samiran Chatterjee, Moumita Mukherjee, Santosh Kumar Chowdhury

Abstract

A compact slotted patch antenna with single layer, single feed suitable for dual-band operations is thoroughly simulated in this paper. By loading properly arranged slots on a rectangular microstrip patch, dual frequency and broadband operations of a single feed rectangular patch is achieved to increase bandwidth performance and also deduced the size of the antenna. The impedance bandwidths of first resonant frequency f1 90.81 MHz with return loss -13.98 dB, second resonant frequency f2 67.68 MHz with return loss -10.11 dB and third resonant frequency f3 720.60 MHz with return loss -16.27 dB are obtained in the proposed design. Where f1 and f2 belong at X-band and f3 belong at Ku-band. By analysis simulated antenna size has been reduced by 79.11% with an increased frequency ratio when compared to a conventional microstrip patch antenna. Here the characteristics of the designed structure are investigated by using MoM based electromagnetic solver, IE3D. An extensive analysis of the return loss, radiation pattern, gain and efficiency of the proposed antenna is shown in this paper. The simple configuration and low profile nature of the proposed antenna leads to easy fabrication and make it suitable for the applications in microwave communication system. Mainly it is developed to operate in the tracking the satellite within the ranges roughly from 12.87 GHz to 14.43 GHz.
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IJECT/34/1/
A-488
   14 A Monopole Printed Antenna for Tracking the Satellite
Bipa Datta, Arnab Das, Samiran Chatterjee, Moumita Mukherjee, Santosh Kumar Chowdhury

Abstract

A single layer monopole slotted patch antenna is thoroughly simulated in this paper. Resonant frequency has been reduced drastically by cutting two properly arrange slots from the conventional microstrip patch antenna. It is shown that the simulated results are in acceptable agreement. More importantly, it is also shown that the differentially-driven microstrip antenna has higher gain of simulated 3.61 dBi at 9.25GHz and -0.52 dBi at 13.65GHz and beamwidth of simulated 164.530 at 9.25GHz and 54.530 at 13.65GHz of the single-ended microstrip antenna. Simulated antenna size has been reduced by 55.49% with an increased frequency ratio when compared to a Conventional microstrip patch antenna.
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IJECT/34/1/
A-489
   15 Improvement of Power Quality by Using 28-Pulse AC-DC Converter
T. Suvarthan Rao, A. Tejasri

Abstract

With the fast growing information technologies, high efficiency AC-DC front-end power supplies are becoming more and more desired in all kinds of distributed power system applications due to the energy conservation consideration for the power factor correction (PFC). For improving power quality in terms of powerfactor correction (PFC), reduced total harmonic distortion at input ac mains and precisely regulated dc output in buck, boost, buck– boost and multilevel modes with unidirectional and bidirectional power flow. This paper presents a new 28-pulse ac-dc converter for enhancing the power quality at the point of common coupling, while feeding a medium capacity switched mode power supply (SMPS). It consists of two series connected 14-pulse ac-dc uncontrolled converters fed by seven phase-shifted ac voltages. The proposed converter is found capable of suppressing up to 27 harmonic currents in the ac mains. The power factor is also improved to near unity over a wide operating range of the SMPS.
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IJECT/34/1/
A-490
   16 Implementation of Digital Campus Security System Based on RFID, ZigBee and GSM
Anil Babu Purella

Abstract

In this paper a digital campus security system (DCST) has been designed and implemented base on the RFID, Zigbee and Gsm network. DCST reads the RFID tags and sends information to pc node through zigbee network and gives alerts through Gsm network. If any invalid RFID(Thief) information comes into pc we will logon the web system to get the real-time tracking for valuables. Where the thief arrives anyone access control node,it would be blocked. User can also manage its own valuables such as lending and recovery operation through the web manager
centre.
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IJECT/34/1/
A-491
   17 A Novel 7-Level Parallel Current Source Inverter for High Power Application with DC Current Balance Control
M. Vamsi Sree, M. R. P. Reddy, CH. Rambabu

Abstract

Multilevel inverters are increasingly being used in high power medium voltage applications when compared to two level inverter due to their merits, such as lower common mode voltage, lower dv/dt, lower harmonics in output voltage and current. Among various modulation techniques for a multilevel inverter, space vector pulse width modulation is poplar due to the merits like, it directly uses the control variable given by the control system and identifies each switching vector as a point in complex space. However the implementation of the SVPWM for a multilevel inverter is complicated. The complexity is due to the difficulty in determining helocation of the reference vector, the calculations of on times and the determination and selection of switching states. The multilevel SVPWM method uses the concepts of two level modulations to calculate the on times of an n-level inverter. Use of multilevel inverters has become popular for motor drive applications. In this paper, a novel Space Vector Modulation is introduced for a 5-level & 7-level parallel current source inverter with DC current balance control is proposed. The method is working by synthesizing the rotating current reference vector in the inverter’s space vector plane with three adjacent switching vectors. One Medium vector is employed as one of adjacent vectors to balance the input DC currents. The switching state for each switching vector is chosen to provide the balanced DC link currents. In addition, lower switching frequency is achievable due to switching design which minimizes the switching loss. Finally, effectiveness of the proposed method is verified by simulation.
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IJECT/34/1/
A-492
   18 Design and Application of Mobile Embedded for Patient Caring Using GPS and RFID
S. Devipriya, Suresh Ballala

Abstract

Biotelemetry is become necessary in today’s world. This article describes about the conclusions acquired in real Biotelemetric system using embedded hardware technology, namely ARM microcontroller, GSM modem, GPS and RFID. Described biotelemetric system is partitioned into logical parts that communicate using GSM and Ethernet protocols.
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IJECT/34/1/
A-493
   19 Development of Unrestricted Text to Speech Synthesis (TTS) System Using Festival Framework for Gujarati Language
Som Sahani, Dr. S. Rama Mohan, Dr. V. H. Pradhan

Abstract

The basic goal of the text to speech (TTS) system is to synthesize the speech for the given input text. TTS is thus an automatic counterpart of a human being loudly reading written text. For physically challenged people with viewing disability, TTS systems will be helpful to communicate with others. Limited domain TTS as the name suggests is built to serve a specific purpose e.g. The TTS used in announcement related queries. Unrestricted TTS system is capable to synthesize good quality of speech in different domains. Festival framework has been used for building the TTS system. In this paper an overview of the technique of Generic TTS is discussed in the first section. Section 2 contains the details of the speech corpus used for developing the TTS. Basic prerequisites and language specific issues needed for building TTS in Gujarati are explained. The technique called Hidden Markov Model (HMM) – based speech synthesis, has been demonstrated to be very effective in synthesizing acceptable speech. The last section in the chapter provides the conclusion of the present work along with future works to be carried out for improving the quality of synthesized speech. As an initial step we have developed a TTS for Gujarati language using phoneme as the basic unit of concatenation.
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IJECT/34/1/
A-494
   20 Visual Cryptography Scheme using Halftone Technique
M. V. Srinivasulu, K. Ramanajaneyulu, Dr. K. Veeraswamy

Abstract

Visual Cryptography (VC), invented by Naor and Shamir [1], is a method for protecting image based secrets that has a computationfree decoding process. Visual cryptography used for sharing visual secrets with multiple secrecy levels in a single image. In the visual secret sharing scheme, a secret image is encoded into shares, of which size is larger than that of secret image and the shares are decoded by stacking them, without performing any cryptographic computation. Extended visual cryptography [2] was proposed to construct meaningful binary images as shares, but the visual quality is poor. In this paper, visual cryptography using half tone technique is proposed by using blue noise dithering principles, the proposed method utilizes the error diffusion algorithms [3-4], to encode a secret binary image into n half tone shares carrying significant visual information. The simulation results shown that, the decoded output gives the secret information with better visual quality than other cryptographic methods. The security properties are also maintained better than in the Region Incrementing Visual Cryptography (RIVC)[5] and Extended visual cryptography[2].
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IJECT/34/1/
A-495
   21 Automation of Proving Testbenches Using Lintchecker
Abhinav Singh, Mehul Kumar, Dr. Arti Noor

Abstract

This paper illustrates the Testbenches and proposes an intelligent checking tool for Testbenches written in SystemVerilog as Lintchecker. Lintchecker can perform various checks on Testbenches prior to simulation and can identify the mistakes which are otherwise hard to detect. Lint evolved as a tool to identify common mistakes programmers made, letting them find the mistakes quickly and efficiently. It is based on Perl. It helps in accelerating verification cycle time and reducing the scope of manual error. This is developed with the objective of automated checking of correctness of a Verification Environment by performing intelligent checks on Testbench code. The tool developed is a rich repository of Universal Verification Methodology and SystemVerilog guidelines and checks the Testbenches within short period of time.
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IJECT/34/1/
A-496
   22 Analysis and Simulation of Intercarrier Interference Due to Phase Noise in OFDM System by Using PLL
Santosh Kumar Gupta, Dr. Geetika Srivastava, Varun Kumar Pandey

Abstract

Orthogonal Frequency Division Multiplexing (OFDM) technique has received a great attention and has been widely used in the wireless communication systems for its high spectrum efficiency and robustness to the narrowband interference and multipath fading. The technique is to divide the channel into many orthogonal subchannels in the frequency domain, and convert the high speed signals to parallel low-speed signals which are transmitted on each sub-channel in parallel with corresponding orthogonal modulated sub-carrier. But it yields however some disadvantages too, one being an increased sensitivity to phase noise, which is generated in the local oscillators. This paper mainly investigate the effect of phase noise upon OFDM system and realized local oscillator (LO)by using phase locked loop (PLL). Then system performance is evaluated as a degradation of the effective signal-to-noise ratio due to phase noise, in terms of BER simulations with and without PLL for different channel conditions.
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IJECT/34/1/
A-497
   23 Design and Characterization of SDRAM Controller IP Core
Arathy S, Nandakumar R, Ashwin P V

Abstract

In modern digital systems large capacity and data transfer rate is required. Synchronous DRAM (SDRAM) become the memory of choice due to its speed, burst access and pipeline features. A Controller is required to provide proper commands for SDRAM initialization, read/write accesses and memory refresh. This paper describes the design of a synthesizable SDRAM Controller IP core which is vendor neutral. The design is described using Verilog HDL, simulated using ModelSim and prototyped in Altera® platform FPGA. Resource utilization and power analysis was done using Altera® Quartus II. Hardware test results are obtained from Signal Tap Logic Analyzer.
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IJECT/34/1/
A-498
   24 Fair and Latency Aware Scheduler for a Voice Over IP Network with Video Conferencing Traffic
Sabyasachi Mukherjee, Sandeep Singh, Paramita Mukherjee

Abstract

In our day to day life scheduling plays an important role for proper execution of any task. We always classify our jobs according to the priority level and then move for execution. Similar is the fact for the routers in any network. Tasks appearing in any router to get served, first be classified according to the priority levels and then be served to maintain quality of service (QoS) of the network. In this paper, an improved scheduling technique has been proposed for Voice over IP network with video conferencing traffic. It has been found that, when weighted fair queuing scheduler is implemented as per the Differentiated Service field, the QoS of the network is quite fair.
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IJECT/34/1/
A-499
   25 A Cost- Effective Low Power Measurement for ZigBee in Wireless Sensor Network
S. Stephen Stainluss, A. S. Vignesh, S. Prabhakaran

Abstract

This paper presents an empirical characterization of battery consumption in commercial 802.15.4 ZigBee motes. This characterization considers various communication operations in 802.15.4 and measures the current that is drained from the power source. Here, the current of a simple Zigbee system with a transmitter and a receiver is measured with the help of an energy measuring scheme. The measurements are being held while these systems operate (either while communicating or while standing idles) and the resulting measurements provide indications of the operations being held. The implemented energy meter circuit is simple. Cost-effective and easy to implement and can be easily integrated with the existing Zigbee network.
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IJECT/34/1/
A-500
   26 An Efficient Cluster Based Approach for Routing Protocol in Mobile Ad-Hoc Networks
B. A. Sarath Manohar Babu, G. Sreedhar Kumar, M. Riyaz Pasha

Abstract

Mobile ad hoc networks are becoming an important concept of modern communication technologies and services. It provides some advantages to this communication world such as self-organizing and decentralization. In this paper, we are going to design a clusterbased multi source multicast routing protocol with new cluster head election, path construction and maintenance techniques. The main objective of this work to compute the maximum performance of proposed routing protocol in various environments, and also it has been compared with Multicast Ad-hoc On-Demand Distance Vector (MAODV) and On-Demand Multicast Routing Protocol (ODMRP) to prove the performance of delivery ratio, control overhead and forwarding efficiency
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IJECT/34/1/
A-501
   27 A Novel Architecture Design & Characterization of CAM Controller IP Core
HimaSara Jacob, Nandakumar. R, Preena Prasad

Abstract

Content Addressable Memory (CAM) is a special purpose Random Access Memory device that can be accessed by searching for data content. This paper describes a novel architecture design and characterization of a reusable soft IP Core for CAM Controller. The proposed design was modeled using Verilog HDL and also prototyped in Xilinx® SPARTAN family FPGA. The power analysis was done using XPower® analyzer and the hardware test result was obtained by ChipScope® Pro logic analyzer.
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IJECT/34/1/
A-502
   28 Power efficient Simulation of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection
Ruchi Singh, C. P. Singh, R. A. Mishra

Abstract

In this paper we have find great applicability in RNS implementation for the Diminished-one modulo 2n+1 Adder using Circular Carry Selection (CCS) circuit. This adder presents a modulo addition of different bit values for n = 8, 12, 16, 24, 32, 48, 64. We are using the Diminished-one criteria using Circular Carry Selection (CCS) technique for the proposed modulo adder. The circuit design of proposed adder consists of a Dual Sum-Carry Look Ahead Adder (DS-CLA), a Circular Carry Generator (CCG) and a Multiplexer (MUX). Results are verified by verilog HDL programs and performance parameters are observed on Synopsys Design Complier using the TSMC (180nm and 90nm) implementation technology. We have calculated the area, power dissipation and Time delay and results are compared with Select-Prefix method for n = 8, 16, 32 and 64 and found that the proposed adder has more area efficient than Select-Prefix Method.
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IJECT/34/1/
A-503
   29 Propagation Characteristics of Surface Plasmon Waves on Semiconductors at Optical Frequencies
Reshmi Maity, Niladri Pratap Maity

Abstract

In this paper the propagation characteristics of Surface Plasmon Waves (SPWs) which exist on the interface of semiconductor and dielectric due to the formation of Surface Plasmon Polaritons (SPPs) at optical frequencies have been evaluated theoretically and simulated. We have considered Ge and Si semiconductors for the purpose. The variation in propagation constant, attenuation coefficient, penetration depth inside the dielectric, penetration depth inside the semiconductor and spot size have been evaluated. It has been found that Si is better than Ge because Si shows more confinement to the SPWs at optical frequencies. For better confinement to the SPWs, the conductivity of the semiconductor can be increased.
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IJECT/34/1/
A-504
   30 Implementation of Real-Time Low-Power Mine Security System Using ARM9
Sravan Kumar Gunturi, Ch. Sridevi, T. V. Janardhana Rao, B. Ch. Kumari

Abstract

Over the years, the threatening condition of production safety in coal mine has been confining the growth of the coal industry, and is also a serious menace to the health and safety of workers in coal mine. So as to acquire the production condition, environment information a kind of Real-Time Low-Power Mine Security System based on the ARM9 board S3C2440 is proposed in this paper. The system can be used to authorize the position of miners and monitor environmental situations in the underground mine, which will increase the level of monitoring production safety and reduce accident in the coal mine. The image acquisition achieved under low-light environment through Webcam. The sensor groups of the system intensively monitor environmental parameters like temperature, light and smoke. It access environmental parameters by RJ-45 interface communication through Ethernet. This system uses web server as a part of a system for monitoring and/ or administering the device like fan. It implements the remote transmission about the information of video, environmental parameters through Ethernet in mine. The experiments show that the Real-Time Low-Power Mine Security System based on ARM9 has low power consumption, intrinsic safety demand and realizes the functions of video monitoring, environmental parameters accessing and network remote transmission.
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IJECT/34/1/
A-505
   31 Implementation of Ultra Low Power 8-Bit CLA and 8-bit ALU CSA Using Single Phase Adiabatic Dynamic Logic
Sweta Mudliar, S. Vasu Krishna, Dr. Sanath Kumar

Abstract

The paper presents the implementation of ultra low power 8-Bit Carry look-ahead adder and 8-Bit ALU-Carry Select Adder circuit operated by Single-Phase Adiabatic Dynamic Logic (SPADL) which, unlike any other existing Adiabatic logic family uses single sinusoidal supply-clock. This not only ensures high energy efficiency, but also simplifies the clock design which would be otherwise more complicated due to the signal synchronization requirement. Static logic resembled characteristics of SPADL logic substantially decreases circuit complexity with improved driving ability and circuit robustness. In TSMC 0.18μm CMOS technology. CADENCE simulations show that SPADL saves 65% to 50% and 30% to 40% of total energy compared to Conventional CMOS and other existing single phase adiabatic logic based 8-Bit ALU Carry Select Adder for a frequency of 1MHz to 100MHz.
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IJECT/34/1/
A-506
   32 A New Converter Topology for Hybrid Power System
S. Ramya, T. Manokaran

Abstract

The objective of this paper is to propose a multi-input power converter for the hybrid system in order to simplify the power system and reduce the cost. The proposed converter interfaces two unidirectional input ports for simultaneously converting two different input power sources with low voltages to a stable output power with a high voltage. Moreover, the demand of bidirectional power flow, which is dependent on the power management for charging and discharging power storage mechanisms, can also be satisfied in a unified structure. It also utilizes four power switches that are controlled independently with four different duty ratios. The renewable power system hybridizes PV and Wind as main source & Battery Power for backup energy source. Three different power operation modes are defined for the converter based on utilization state of the battery as follows: 1)An operation type wherein power is delivered to load from hybrid renewable energy sources; 2)A single type wherein only one renewable energy source supplies power to the load with battery discharging; 3) An operation type wherein power is delivered to load from renewable sources along with battery charging. A simple and cost effective control with DC-DC converter is used for maximum power point tracking (MPPT) and hence maximum power is extracted from the source .The integration of the hybrid renewable power system is implemented and simulated using MATLAB/SIMULINK.
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IJECT/34/1/
A-507
   33 Optimisation of Metal Gate Workfunction Engineering for the Deep Sub-Micron MOSFET’s
Farkhanda Ana, Najeeb-Ud-Din

Abstract

The continued scaling of the devices towards the deep submicrometer regime has undoubtedly lead to improved performance, thus flooding the market with miniaturized devices. The device scaling increases the chip density per unit area within a year or 18 months according to the Moore’s law. This scaling is the success story behind Intel’s present generation i7 processors. With the device dimensions reaching nanometer node, the conventionally used polysilicon gates are being replaced by the metal gates. Even the Silicon-on-Insulator devices and Ultra thin body (UTB) devices show improved performance using metal gate devices. The threshold voltage fluctuations of UTB devices are also eliminated by changing the gate work function. Metal gated devices show reduced leakage, improved transconductance and are more compatible with high-k gate dielectrics. This paper presents a brief description of the metal gate technology followed by studying the effect of using metal gate on device performance.
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IJECT/34/1/
A-508
   34 Lip Based Recognition: A Comparative Analysis
M Haider Mehraj, Ajaz Hussain Mir

Abstract

There is an increasing requirement for robust and reliable person authentication systems in areas of high security or secure access. The majority of current techniques for person recognition focus on either static facial information or speaker recognition via the speech signal. Whilst in clean conditions, the speech signal has proved to be a valuable source of speaker dependent information, problems occur in noisy or channel mismatch conditions. Whilst lip information presents predominantly speech dependent information, valuable speaker dependent information is also contained within the static and dynamic features of the lips. This paper presents a comparative review of various lip based biometric techniques and makes comparisons between them by using Relative Operating Characteristics (ROC) curve and Recognition Time (RT) as performance metric. The ROC curve and recognition time has been obtained at varying frame rates to determine the best lip recognition technique.
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IJECT/34/1/
A-509
   35 Conducted EMI Reduction for Grid Connected Paralleled Solar Power Inverters
Atul Gupta, Venu Uppuluri, Mangesh Kadam, Akash Sharma, Anurag Porippireddi

Abstract

This paper introduces a distributed approach for interleaving paralleled power converter to reduce EMI and voltage ripple, accomplished via IEEE 1588 Precision time protocol. An open source stack of IEEE 1588v2 named PTPd-2.2.0 is used to implement software stack over stellaris series microcontroller from Texas Instruments (TI). A general methodology for achieving distributed interleaving is proposed, along with a specific implementation approach using the PTPdv2. The effectiveness of such methods in terms of EMI reduction is experimentally validated in grid connected Paralleled Solar Power Inverters.
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IJECT/34/1/
A-510
   36 Effect of Subsetting of FCC Image on the Accuracy of the Classified Image
Satyanarayana Chanagala, Yedukondalu Kamatham, Appala Raju Uppala, Najeemulla Baig

Abstract

Remotely sensed image raw-data gathered by a satellite or aircraft needs to be corrected. Even images of seemingly flat areas are distorted by both the curvature of the Earth and the sensor being used. Hence there is a need for geometrically correcting an image. For this work data from satellite image (IRS –P6) by LISS-III sensor of 5.8m resolution is used. This image corresponds to Ramtek region of Nagpur (Maharashtra state of India). This raw FCC image is preprocessed which includes importing, subsetting and Georeferencing and then extracting the useful information by supervised classification and then performing the accuracy analysis. After doing the accuracy analysis, emphasis is made on further improving the accuracy of the classified image. In this regard, the rectified FCC is divided into subsets while making the number of classes constant for each subset. Then accuracy analysis is performed on each subset of rectified FCC, followed by accuracy analysis. Then the accuracy of the classified image before subsetting is compared with the accuracies of the classified subset images is performed. The results obtained showed a decrement in the accuracy after subsetting, which was not expected. The reasons for the same are investigated in this paper.
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IJECT/34/1/
A-511
   37 Power Optimization of System-on-Chip Communications in VLSI Chips
P. Sreenivasulu, Mahalakshmi, Dr. K. Srinivasa Rao, Dr. A. Vinaya Babu

Abstract

Consumption of power and the thermal wall have become the major factors that are limiting the speed of Very-Large-Scale Integration (VLSI) circuits, while interconnect is becoming a primary power consumer. These factors bring new demands on the communication architecture of Ssystem-on-Chips (SoCs). With expertise in low power tools and techniques, Synopsys consultants can help you manage the chip dynamic and leakage power consumption. The paper will help to understand the inherent tradeoffs in using power-related technologies such as voltage islands, power and clock gating, multi-voltage design, dynamic voltage scaling, multiple threshold voltages,. With project requirements in mind, our consultants can then assist to deploying the latest low-power techniques throughout the entire design flow, from synthesis, to functional verification and clock tree synthesis, through implementation and post-route in this paper optimization of Low power logic synthesis show 10% power saving for synthesis block. System power management is used to monitor the system activity and enforce the movement of the system components between different power states.Software based power reduction this is CPU power consumption is dominated by a large cost factor (clock, caches, etc.) that for the most part, does not vary much from one cycle to the other.
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IJECT/34/1/
A-512
   38 Complementary Metal–Oxide–Semiconductor (CMOS) Upgraded Utilities
P. Srinivas, P. Balakrishna

Abstract

The trends in modern digital systems will be increasingly focused on design solutions that are high in reliability and low in cost. Performance requirements and power restrictions will continue to be major factors. However, design verification and reliability are becoming two critical design cost components. Parallel multiplication has been one of the most important operations in digital signal and image processing, specifically in application such as digital video, digital baseband for telecom, high speed graphics, etc. We present a high-speed wide-range parallel counter that achieves high operating frequencies through a novel pipeline partitioning methodology (a counting path and state look-ahead path), using only three simple repeated CMOS-logic module types: an initial module generates anticipated counting states for higher significant bit modules through the state look-ahead path, simple D-type flip-flops, and 2-bit counters. The state look-ahead path prepares the counting path’s next counter state prior to the clock edge such that the clock edge triggers all modules simultaneously, thus concurrently updating the count state with a uniform delay at all counting path modules/stages with respect to the clock edge.
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IJECT/34/1/
A-513